From a practical standpoint, there are two conditions which must be satisfied in order for VLSI circuit fabrication to continue to be a useful, burgeoning technology. First, the fabricated circuits must be capable of being produced in large quantities at costs which are competitive with alternative methods of achieving the same circuit and system functionality. Second, the circuits must be capable of performing their functions throughout their intended useful life.
In order to deal successfully with these two requirements, various methods have been developed to identify the diverse mechanisms which seriously limit the yield and reliability of VLSI circuits. Likewise, prodigious attempts have been made at developing accurate yield and reliability modeling parameters to enable the manufacturer of VLSI circuits to better predict the reliability of his product. Economically, it is very critical for the circuit fabricator to be able to detect those integrated circuits of a certain class which are unreliable due to a particular type of reliability failure mechanism.
Ideally, in a properly fabricated wafer of integrated circuits, one would expect all of the circuits to be good functional devices. However, in practice, the number of good circuits per wafer may range anywhere from 0 to 100%, depending on the process employed and the relative complexity of the circuit. The causes for less than perfect yield often depend on the category or class of ICs which is being fabricated. For instance, low yield and reliability may be due to parametic processing problems, circuit design problems or random point defects in the circuit.
One class of integrated circuits contain floating-gate memory devices which utilize electron tunneling to either add electrons to, or remove electrons from, the floating gates. In other words, electron tunnelling is employed to either program and/or erase those cells. Such ICs are often called EEPROMs, E.sup.2 PROMSs, flash EPROMs, or non-volatile RAMS. Floating gate cells which rely on tunnelling may also be used in other types of integrated circuits as well.
One predominant reliability failure mechanism has plagued floating gate devices in the past. This specific mechanism involves the dielectric breakdown of the dielectric through which electrons tunnel during programming and/or erasing operations. This dielectric is commonly referred to as the tunnel or gate oxide. Following dielectric breakdown, the oxide separating the floating gate from the substrate no longer behaves as an insulating material. As a result, electrons previously programmed into the floating gate do not remain there in the course of the normal operation of the device. Instead, these electrons "leak" off of the floating gate--tunneling their way back to the substrate.
As is appreciated by practioners in the art, loss of electrons from the floating gate dramatically affects data retention rates in such devices. By way of example, int he case of flash EPRONMs submicroscopic defects in the tunnel oxide near the drain region leads to premature dielectric breakdown; often 10 to 100 times sooner than would normally be the case. Such breakdown usually occurs after repeated program/erase cycling of the IC. The ability of an EPROM-type device to survive such cycling is called the IC's "reliability" or "endurance". An IC failing after a given cycling operation is frequently referred to as suffering an "endurance failure".
Note that the term "reliability" as used in this context, refers to the probability that an IC will perform a required function for a stated period of time. For floating gate memory device, the "required function" is generally defined as its ability to cycle a given number of times. For example, properly fabricated EEPROMs and flash EPROMs are generally expected to cycle anywhere between 10,000 and 100,000 times before experiencing endurance failure.
In the past, once a floating-gate circuit has been completely fabricated, there has no been a way of predicting how many cycles that part may endure before suffering destructive dielectric breakdown. Consequently, manufacturers have had to implement elaborate screening procedures to eliminate those devices which are destined to bail within a relatively short period of time. The traditional method of screening dielectric breakdown endurance failures involves extensive program/erase cycling of the ICs. The devices in question, or a statistical sample of them, are cycled many times and then tested for proper functionality, which usually includes a test for data retention. This type of screening generally involves discarding the failed ICs. Alternatively, the IC may be repaired using redundant circuitry which can be switched in to replace defective circuit elements. Lot/acceptance criteria may also be used so that an entire lot of wafers may be rejected based upon the percent fail in the cycling screen or some other measure of endurance of the lot or the samples taken from it.
This method is not without its disadvantages. For instance, the cycling test is quite expensive and time consuming; often typing up expensive test equipment. Moreover, when used with a lot-acceptance criteria, the cycling method requires rejecting reliable ICs along with unreliable ones (since even an "unreliable" lot may consist of 90% reliable ICs). Furthermore, when used as a 100% test to screen all material of unreliable ICs, the cycling method has all of the disadvantages inherent to any "aging" screen. Cycling ages all integrated circuits equally, Thus both reliable and unreliable devices are aged in the effort to detect those ICs which are destined to fail at an early age. Obviously, this reduces the useable lifetime of the reliable devices.
In certain circumstances, cycling screen also inherently depends upon the assumption that the IC populations failure rate is a decreasing function of the number of cycles; otherwise, the cycling screen would increase rather than decrease the failure rate. In those instances where the failure rate decreases slowly as a function of the number of cycles, achieving endurance goals may require excessive cycling and resultant yield loss. Therefore, such screens work best when there exists a very discrete infant mortality population. Unfortunately, this has not traditionally been in case for EEPROM-related devices. Accordingly, manufactures have been forced to perform cycling to eliminate most failure problems while excepting the risk that a significant number of the remaining ICs (i.e., those passing the screening test) may prove unreliable in future use.
Another existing method to reduce the dielectric breakdown endurance problem is through error correction; often modified Hamming-code error correction. This involves using extra error correction cells (i.e., parity bits) to store redundant information sufficient to reconstruct the correct data when one of the floating gate cells suffers dielectric breakdown. Error correction can either be built directly into the integrated circuit design or incorporated into the external system environment by the user of the integrated circuit device.
The error correction methods are generally effective but expensive. Error correction schemes require additional floating gate cells to store the redundant error correction information. For byte-level error correction, this requires a 50% increase in the number of floating gate cells. In other words, 12 memory cells are required for every 8 bits of data to be stored. When built into the integrated circuit itself, error correction requires additional support circuitry which is expensive and which can reduce the overall speed of the integrated circuit (since correcting errors takes additional time). Incorporated into the system environment, error correction also increases the complexity and cost of the system.
Accordingly, one object of the present invention is to provide a cost-effective way of detecting those floating gate integrated circuits which are destined to early failure due to premature breakdown of the tunnel dielectric.
It is another object of the present invention to provide a means of screening floating-gate ICs employing tunneling for programming and/or erasing for dielectric breakdown endurance failures.
It is yet another object of the present invention to provide a means for statistically predicting the useful life of an EPROM-type integrated circuit.